Chipsets requiring multiple power supplies or operating voltages are very common. Such chipsets can be complex and include several millions of transistors, covering Radio Frequency (RF) and analog base band platforms. Many designers who design big D/big A chipsets have a digital centric top-down flow. More particularly, the design starts with a high level type of module description (e.g., in SystemC, SystemVerilog, or Verilog/VHDL), which leads to a lower level, synthesizable Register Transfer Level (RTL) code for defining digital circuits. The RTL specifications are used to generate gate-level netlists. It is important to verify that various blocks of the circuit design are correctly connected to particular power supplies so that the circuit design operates as intended. However, after circuit synthesis, digital blocks that require different supply sensitivity are often scattered all over the chip, which can complicate verifying that particular blocks are connected to the correct supply.
In cases in which all of the digital modules use the same supply sensitivity, then verification is straight forward and can be completed using, for example, “event” driven simulators. However, in most cases, chipsets use multiple supply sensitivities and, therefore, it can be very difficult to verify connectivity and functionality of multiple different supplies with known digital simulators. For example, a typical “2.5G” platform chipset includes modules such as “smartPOWER, DSP core, ARM core, global switching module, etc”. Each module has two to three supply voltages and uses schemes such as “state-retention” techniques. It is important to verify the functionality of these “modules” not only as a function of their inputs, but also as a function of their supply-domains. These tasks must account for a large number of transistors, e.g., 30 million or more transistors, after the synthesis has been performed. Using conventional verification approaches for this purpose can be very difficult.
In order to address these difficulties, designers often defer such checks to transistor level verification using technologies such as fastSPICE/fastMOS. One shortcoming of these known approaches, however, is that they require substantial simulation time and computing resources. Further, they may not be able to cover the required portions of the circuit design. Another known technique designers have used to reduce costs is verifying only critical design paths. However, these known techniques can impact verification quality.
Since there is no acceptable technique that can quickly and accurately verify power supply connectivity in chip sets, designers have often resorted to “fooling” simulators. For example, one known technique is to use “stubs” to blank out cells and create multiple such configurations to verify chip functionality in bits and pieces. This is otherwise known as “manual partitioning.” However, the interdependencies between such cells are ignored since it is time-consuming to add meaningful behavioral constructs to these stubs to capture the functionality. Another known technique involves verification leads writing “analog-behavioral” models and using these models to speed up simulations and capture basic functionality. However, functional coverage using this technique can be improved, and it can be difficult to calibrate an analog-behavioral model with a SPICE netlist.
Thus, known verification techniques suffer from a number of shortcomings, including performing simulations to verify correct supply connectivities, requiring design modifications and performing verifications with reduced or unsatisfactory functional coverage. Further, known verifications techniques may not follow standards, require specific designs, and increased verification costs and time, leading to inefficient verifications.
Accordingly, there exists a need for a method of allowing designers to complete circuit verifications in a time and cost efficient manner without running simulations, while achieving the desired functional coverage. Embodiments of the invention fulfill these unmet needs.